(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual Sixe2x80x94Ge polysilicon gates having different Ge concentrations in the fabrication of integrated circuits.
(2) Description of the Prior Art
Silicon-Germanium (Sixe2x80x94Ge) polycrystalline gates have advantages over conventional silicon polycrystalline gates. Lee et al in xe2x80x9cInvestigation of poly-Si1xe2x88x92xGex for dual-gate CMOS technology,xe2x80x9d IEEE EDL, p. 247, 1998 and in xe2x80x9cObservation of reduced boron penetration and gate depletion for poly-Si0.8Ge0.2 gated PMOS devices,xe2x80x9d IEEE EDL, p.9, 1999 have reported that polysilicon-gate depletion (PD) effect and boron penetration effect for PMOS devices is reduced with increasing Ge concentration, while NMOS devices with approximately 20% Ge concentration exhibit the least PD effect. Later, in xe2x80x9cEnhancement of PMOS device performance with poly-SiGe gatexe2x80x9d, IEEE EDL, p. 232, 1999, Lee et al reported that the hole""s mobility for PMOS devices with Sixe2x80x94Ge poly is higher than those devices with Si-poly.
In xe2x80x9cWork function of boron-doped polycrystalline SixGe1xe2x88x92x filmsxe2x80x9d, IEEE EDL, p. 456, 1997, Hellberg et al reported that the work function for p+-doped SiGe polycrystalline film decreases as the Ge content increases. Hence, it is possible to improve the CMOS device performance by using gate work function engineering coupled with super-steep retrograde channel engineering (xe2x80x9cHigh-performance deep submicron CMOS technologies with polycrystalline-SiGe gates,xe2x80x9d Ponomarev et al, IEEE ED, p. 848, 2000) or lateral channel engineering (xe2x80x9cA 0.13 xcexcm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications,xe2x80x9d Ponomarev et al, IEEE ED, p. 1507, 2000)
Ponomarev et al in xe2x80x9cGate workfunction engineering using poly-(SiGe) for high performance 0.18 xcexcm CMOS technology,xe2x80x9d IEDM, p. 829, 1997, reported that a buffer poly-Si layer can be introduced on the Sixe2x80x94Ge poly gate to preserve the standard salicidation scheme. Uejima et al in xe2x80x9cHighly reliable poly-SiGe/amorphous-Si gate CMOSxe2x80x9d, IEDM, p. 60, 2000, reported that gate oxide reliability can be improved by adding a thin amorphous silicon layer prior to Sixe2x80x94Ge polysilicon deposition.
Since it is desirable to have about 20% and about 50% Ge for NMOS and PMOS devices, respectively, in order to achieve the optimum performance for CMOSFET""s, it is desired to provide a method for forming a dual Sixe2x80x94Ge poly-gate CMOSFET with different Ge concentrations for NMOS and PMOS devices.
U.S. Pat. No. 6,326,252 B1 to Kim et al, U.S. Pat. No. 6,303,418 B1 to Cha et al, and U.S. Pat. No. 6,323,115 B1 to Tanabe et al disclose dual gate processes. U.S. Pat. No. 6,200,866 B1 to Ma et al shows a replacement gate process using SiGe as the dummy gate material.
Accordingly, a primary object of the invention is to provide a process for forming dual Sixe2x80x94Ge poly-gates in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual Sixe2x80x94Ge poly-gates having different Ge concentrations in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming dual Sixe2x80x94Ge poly-gates having different Ge concentrations for NMOS and PMOS devices in the fabrication of integrated circuits.
Yet another object of the invention is to provide a process for forming dual Sixe2x80x94Ge poly-gates having different Ge concentrations for NMOS and PMOS devices using blanket Sixe2x80x94Ge polysilicon deposition followed by selective Ge implantation in the PMOS region.
In accordance with the objects of the invention, a method for forming a dual Sixe2x80x94Ge poly-gates having different Ge concentrations is achieved. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Sixe2x80x94Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Sixe2x80x94Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Sixe2x80x94Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Sixe2x80x94Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.